Current data processing systems using the S/390 architecture directly transfer data between I/O and MS. But they only indirectly transfer data between I/O and ES, which involves an I/O-MS transfer controlled by an I/O channel processor, and an MS-ES transfer controlled by a central processor (CPU) or by a data mover (ADM) using a channel processor.
An example of an ES to I/O data transfer occurs when ES storage space is to be freed up by moving pages of data out of ES to I/O. An example of an I/O to ES transfer occurs when a system is more efficiently operated by moving data pages into its fast ES electronic storage from slower electro-mechanical I/O devices, so that the system can quickly access the data in ES.
Under current S/390 architecture, channel programs comprise CCWs (channel control words) and IDAWs (indirect data address words), and channel programs can only control data transfers to/from MS.
A CPU page-in instruction and a page-out instruction for synchronously controlling ES/MS data transfers are disclosed and claimed in U.S. Pat. No. 4,476,524 to Brown et al using real addressing in MS, which is assigned to the same assignee as the subject application. A move page (MVPG) instruction for synchronously controlling ES/MS data transfers, and capable of using virtual addresses in MS, is disclosed and claimed in U.S. Pat. No. 5,237,668 by Blandy et al., published Aug. 19, 1993, filed Oct. 20, 1989. Also, transfers between ES and MS may be asynchronously controlled by a CPU using request-response instructions of the type disclosed and claimed in U.S. Pat. No. 5,386,560 by McCauley et al., published Jan. 31, 1995, entitled "Split Instruction Paging Method and Means". Another proposal is found in a European patent application 0 214 870 having priority date of Dec. 9, 1985.
Channel programs have been proposed for controlling transfers of data between ES and MS as in U.S. Pat. No. 4,476,524 to Brown et al using real addressing, and in U.S. patent application Ser. No. 07/816917 filed Jan. 3, 1992 by Dewkett et al entitled "Asynchronous co-processor method and means", now abandoned Jun. 15, 1995.
Data transfers between I/O and ES without passing through MS are understood to be proposed in a Japanese patent specification number 62-212744 published, on Sep. 18, 1987, which (as best can be understood from an English abstract of the specification, and its drawings) discloses a specific prescribed channel-command-word (CCW) to control a direct transfer of data from an external memory device to ES (expanded storage). A control bit is provided in a start subchannel operation to indicate that the specific prescribed CCW is used in a channel program addressed by the subchannel in MS to control a direct data transfer from an external memory device to ES. The specific prescribed CCW, itself, does not specify any data transfer, but it only specifies a change of mode in the channel program to enable subsequent CCWs in the channel program to access ES. Only CCW(s) which follow the specific prescribed CCW in the channel program can specify data transfers between the external device and ES. Before a later data transfer to MS may be made by the external device, the subchannel mode must again be changed to MS mode, which may perhaps be done by using a conventional transfer-in-channel (TIC) CCW that transfers channel control to another channel program which may be non-contiguous in MS with its preceding channel program. Then, such a TIC CCW is followed by conventional CCWs that specify data transfers between the external device and MS.
Accordingly, the Japanese specification is understood to require a subchannel to switch mode (to either ES mode or MS mode) in a different channel program in order to enable an I/O-ES transfer or an I/O-MS transfer. Switching modes for different channel programs involves additional channel overhead and reduces system performance. The Japanese patent does not use any indirect-data-addressing words (IDAWs) in its ES transfer controls.